The scaling approach that has been the technological mainstay of the semiconductor industry for the last 30 years is beginning to face limits to continued miniaturization with commensurate performance enhancement. Prof. Saraswat has been working on new and innovative materials, structures, and process technology of semiconductor devices and interconnects for VLSI and nanoelectronics. Areas of his current interest are: new device structures and materials to improve solar cell efficiency and lower cost, continue scaling MOS transistors to nanometer regime, 3-dimentional ICs with multiple layers of heterogeneous devices, and optical interconnections.

RECENT MAJOR PROJECTS:

Materials, Structures, Devices Physics and Technology for Nanoelectronics

Si CMOS technology has dominated the microelectronics industry, with continued scaling. However, future Si CMOS scaling is reaching practical and fundamental limits. To go beyond these limits novel materials and structures are being aggressively studied. A channel material with high µ and therefore high injection velocity can increase drive current and reduce delay. Currently, strained-Si is the dominant technology for high performance MOSFETs and increasing the strain provides a viable solution to scaling. However, performance enhancement due to strain is beginning to saturate with scaling of nanoscale MOSFETs. Looking into future scaling it becomes important to look at higher mobility materials, like Ge and III-V together with innovative device structures which may perform better than even very highly strained Si. Heterogeneous integration of the high mobility Ge and III-V materials on Si with novel device structures can take us to sub-10 nm regime. However there are many daunting questions. Ge PMOS shows much promise but the NMOS has many problems to be solved. Similarly there are many examples of high performance III-V NMOS, but PMOS is still problematic. Is Ge PMOS and III-V NMOS integration on Si feasible or a headache for the manufacturing folks? Can we have all Ge or all III-V CMOS or it is just a fantasy? Prof. SaraswatÕs research is trying to answer these questions.

Interconnects for Nanoelectronics

Continuous scaling of VLSI circuits can pose significant problems for interconnects, especially for those responsible for long distance communication on a high performance chip. Our modeling predicts that the situation is worse than anticipated in the ITRS, which assumes that the resistivity of copper will not change appreciably with scaling in the future. We show that resistance of interconnect wires in light of scaling induced increase in electron surface scattering, fractional cross section area occupied by the high resistivity barrier and realistic interconnect operation temperature will lead to a significant rise in the effective resistivity of Cu. As a result both power and delay of these interconnects is likely to rise significantly in the future. In the light of various metal interconnect limitations, alternate solutions need to be pursued. His group focuses on two such solutions, optical interconnects and three-dimensional (3-D) ICs with multiple active Si layers.

Photovoltaics

High Efficiency attribute of solar cells is a powerful enabler to reduce the $/Wp metric by cutting across the entire PV supply chain. In addition, a higher efficiency cell, especially if it is higher Voc, can result in a much larger energy yield (KWHr/KWp) per given efficiency or peak power. These factors go a long way in enabling the goals set by U.S. Department of Energy of 1. delivering modules at under $0.40/W, 2. reducing the BOS cost, 3. ultimately achieving an LCOE of 5 cents/KWhr. To meet these requirements we are developing a novel junctionless solar cell using metal/insulator/semiconductor (MIS) structures as carrier selective contacts on Si, GaAs and other absorbers.

RECENT Ph.D. STUDENTS:

Jung-Soo Ko, Ph.D. 2024
Research: Gate Dielectric for FETs in 2D TMD Materials

Nanoelectronic devices based on 2D materials are far from delivering their full theoretical performance potential due to the lack of scalable insulators. Most of the published work on MOSFETs in TMDs uses a back gate approach with relatively thick SiO2 gate dielectric. For adoption of nanoscale MOSFETs in TMDs in a manufacturing process a top gate structure with ultrathin gate dielectric with higher dielectric constant is needed. The dielectrics in general have defect bands. If these defect bands lie within the bandgap of the 2D TMD they will have detrimental effect on the electrical characteristics. By choosing a dielectric such that the defect bands lie outside the bandgap of the 2D TMD the detrimental effects can be eliminated. Currently the industry is ALD for incorporating gate dielectric. Due to lack of dangling bonds at the surface of 2D TMDs, it is difficult to perform ALD which is essential for ultra-thin film deposition. For this reason, seed layer for ALD nucleation is needed for gate stack on 2D TMDs to achieve low equivalent oxide thickness devices. The seed layer should have the defect band. For example, within our group, English et al. reported thin Al seed layer deposition on 2D MoS2 and found ~1.5 nm of electron beam evaporated Al does not degrade the mobility of the channel and at the same time transforms into AlOx that can act as ALD nucleation seeding layer. In this work we propose to achieve ultra-thin EOT, down to 1 nm.

Marc Jaikissoon, Ph.D. 2023
Research: Stressor Films for 2D Materials.

We propose the use of CMOS-compatible stressor layers such as SiNx to induce strain in 1L-MoS2 to increase transistor performance in pursuit of the IRDS requirement for on-current of 1 mA/um. To this end, we propose to investigate highly stressed films such as SiNx, Al2O3 and HfO2. Several commonly used thin films in nanofabrication contain appreciable levels of stress measured by wafer curvature. We propose to fabricate FETs capped by these films in both back and top-gated architectures to establish the effect of stress and its dependence on geometry and critical dimension. The stress in these films can be tailored through the variation of process parameters such as temperature or pressure, allowing for the degree of stress to be controlled. In addition to FET fabrication, measurements of the MoS2 lattice constant when capped by these films will be performed via grazing incidence x-ray diffraction measurements as well as Raman spectrum analysis in order to correlate to device performance. In addition to the strain induced by capping layers, we propose to study the strain which may be induced during deposition of the metal contacts. Ni contacts have been commonly used to achieve low contact resistances to MoS2 FETs, but the contribution of strain has not been investigated and offers room to further lower the contact resistance toward the target value of 100 ohm.um. We will fabricate FETs with various thicknesses of contact metals and perform temperature dependent measurements to extract the Schottky barrier height in order to establish the effect of strain on carrier injection. Additionally, Raman measurements can be performed after incremental steps of metal deposition to correlate the potential tensile strain in the MoS2 channel caused by the stressed metal contact.

Arvindh Kumar, Ph.D. 2022
Research: Low Resistance Contacts to 2D Transition Metal Dichalcogenides (TMD) MOSFETs.

Monolayer 2D TMDs such as MoS2 and WS2 (~0.6 nm thick) are promising candidates for sub-10 nm channel transistors, which need an ultrathin channel to maintain the gate electrostatic control. 2D TMDs have good mobility in such ultrathin channels, whereas traditional semiconductors like Si and Ge face severe mobility degradation due to surface roughness. The electrical performance of short-channel TMD transistors is, however, limited by the high resistance of the Schottky contacts. Our goal is to is to improve contact resistance to less than 100 ohm.um in n- and p-channel MOSFETs in 2D TMDs by utilizing alloys of soft metals (In, Sn or Bi) with stable, CMOS compatible hard metals like Pt or Ni, while also developing a thorough understanding of the physics at the interface and the compatibility of the contacts with CMOS back-end processing thermal budgets. Our recent research found that metals with higher melting point caused defective MoS2, while metals with lower melting point indicates less damage during the metal evaporation. In preliminary work, we also fabricated NFETs with alloyed In/Au and Sn/Au contacts to MoS2 and obtained RC as low as 190 ohm.um and 270 ohm.um, respectively. Our analysis revealed that In or Sn alloys with Au, created intermetallic phases which have a higher temperature tolerance that is compatible with back-end processing thermal budgets. In contrast, individual soft metals like In, Sn, and Bi are incompatible with CMOS processing, as their melting points are less than 270 C. However, Au is incompatible with CMOS processing. We will develop this technique to use CMOS-compatible alloying metals like Ni or Pt instead of Au in order to make this technique manufacturable.

Koosha Nassiri Nazif, Ph.D. 2021
Research: Transition Metal Dichalcogenides (TMDs) for Next-Generation Photovoltaics.

The incumbent silicon solar cells are reaching their performance limits. Silicon therefore needs to be augmented or replaced with new photovoltaic materials to either achieve higher power conversion efficiency (at low cost) or fit emerging applications in wearable electronics, unmanned aerial vehicles, and electric cars. Semiconducting transition metal dichalcogenides (TMDs) are promising candidates for next-generation photovoltaics due to their ultrahigh absorption coefficients, desirable band gaps, high stability, and biocompatibility. However, challenges such as Fermi-level pinning at the contacts and the inapplicability of traditional doping schemes have prevented most TMD solar cells from exceeding 2% power conversion efficiency. In this talk, I will show how we addressed some of the main challenges in TMD photovoltaics using molybdenum oxide (MoOx) doping, passivation, and anti-reflection coating, van der Waals graphene contacts, and novel methods to transfer TMDs onto rigid and flexible substrates. I will then show how these solutions led to record high performance levels in TMD solar cells on par with prevailing thin-film solar cell technologies, and how we can aim for even higher performance with more optimized optical and electronic designs.

Pranav Ramesh, Ph.D. 2021
Research: Metal/Insulator/Semiconductor Contacts for Photovoltics and Nanoelectronics.

As device scaling continues, parasitic source resistance largely dominated by contact resistance, is beginning to limit the device performance. Specific contact resistivity of a metal-semiconductor (M/S) contact is dependent on the Schottky barrier height, and the electrically active dopant density N at that interface. In M/S contacts the metal Fermi level is pinned at the charge neutrality level, ECNL, resulting in fixed electron and hole Schottky barrier heights. To obtain low contact resistivity it is essential to reduce Schottky barrier height. Historically the method to reduce contact resistivity is by increasing N to > 1E20/cm3 thereby thinning the barrier, thus allowing more tunneling current. This method works well for n type Si and p-Ge which can be doped heavily. However, it is not very practical for n-Ge, p-Si, many III-Vs and 2D materials because of inability to dope them heavily. We are investigating Fermi level depinning by inserting a thin dielectric between the metal and semiconductor and reduce barrier height. The metal electron wavefunction now decays in the insulator resulting in fewer MIGS thus depinning the Fermi level, which now pins on the insulator. Hence metal workfunction can now be used to tune the effective barrier height. For n-type ohmic contacts, metals with a low metal workfunction and insulator with ~0 conduction band offset (ZnO, TiO2, SnO2) with semiconductor should result in a near zero barrier height to electrons. For p-type ohmic contacts, metals with a high work function and insulator with ~0 valence band offset (NiO, CuAlO2) with semiconductor would be desirable. This method has been used to obtain low barrier height and thus low contact resistivity in Si, Ge and III-V semiconductors and should prove to be very useful for 2D materials.

Stephanie Tietz, Ph.D. 2021
Research: Advancing Communication through Novel 3D Silicon Photonic Devices

In device technology, there is a drive to make everything smaller, from the chips in handheld devices to the sensors in wearables. Yet research shows that achieving smaller dimensions can come at a high price. For integrated circuits, this price comes from burgeoning issues like high resistance and capacitance when the copper wires used as electronic interconnects become thinner and more closely packed together on a chip. One way to combat the size limit facing the semiconductor industry is to exploit silicon photonics. This work shows how to improve communication capabilities by harnessing the full power of silicon photonics, and particularly the resiliency provided by photonic crystal devices. We explore a novel fabrication technique that led to the first truly Silicon-compatible three-dimensional (3D) photonic crystal. While this 3D photonic crystal alone acts as a broadband omnidirectional reflector, we demonstrate how this versatile fabrication methodology can be slightly modified to create a multitude of devices including 3D waveguides and 3D cavities. Applications for these silicon photonic crystal devices range from solar cells to sensing, but this work focuses on their use in integrated circuits to help the semiconductor industry progress to even smaller dimensions.

Junkyo Suh, Ph.D. 2020
Research: SiGe/Ge Nanowire Platform for Nanoelectronics and Nanophotonics

In this work, we present a novel approach to build SiGe/Ge nanowire platform along with device demonstrations for advanced high-performance transistors and nano-photonic devices. The proposed method exploits CMOS technology and meets the requirements of high mobility material incorporation, 3D-stacking, and multi-gate controllability. Innovative techniques and solutions to various challenges will be presented to address the following topics:

3D-stacked SiGe/Ge Gate-All-Around (GAA) Device Architecture Ð Stacked nanowires (NWs) and/or nanosheets (NSs) devices are promising to gain performance and power benefits. 3D local Ge condensation is utilized to not only incorporate Ge as a high mobility channel material, but also introduce strain to the channels which is beneficial for even higher mobility.

Low Resistance Contact to n-Ge Ð Forming a low barrier junction between metal and n-Ge is critical to achieve high performance Ge nFETs, which is difficult due to Fermi-level pinning. Our method utilizes III-V as an insertion layer to construct hetero-contacts, which allows us to Òre-directÓ the location of Fermi-level pinning to a more favorable position. As a result, 60X improvement is accomplished at a moderate doping concentration.

Suspended Nanowires above Si Substrate Ð 3D stackability of NWs above Si sub. opens up opportunities to make new optically resonant devices. By stacking 2NWs, optical molecules can be formed with strong optical coupling and the vertical stacking allows more modes to be excited under top illumination due to phase delay created between NWs. In addition, suspended NWs offer engineering opportunities to tune spectral response by changing dielectric environment around the devices, which is realized by filling the cavity with various refractive index media.

Archana Kumar, Ph.D. 2018
Research: Scaled antimonide p-MOSFETs and their hetero-integration on silicon

Antimonides are a promising group of III-V compound semiconductors being actively researched for high-speed low-power digital CMOS as well as for THz/mm wave devices. They have the highest hole mobility among all III-Vs and are the only viable candidate for a high-performance III-V p-MOSFET. They also have high electron mobility and could enable an all-antimonide CMOS solution. This work first addresses the most critical challenge of III-V technology Ð hetero-integration on silicon. Rapid-melt-growth (RMG) technique for the hetero-integration of GaSb on a silicon substrate is studied. A low-temperature MBE process is developed to obtain pure, amorphous GaSb which is then melt-regrown into scaled high-quality single crystal fins. GaSb-on-insulator p-MOSFETs are successfully demonstrated and factors limiting device performance are identified. In parallel, quantum-well heterostructures were grown by the more established technique of metamorphic buffer growth using MBE to obtain high-performance antimonide p-MOSFETs. Two different device structures are compared Ð a buried channel structure and a surface channel structure. Scaled devices with ~100 nm gate length metal gate/high-k dielectric and self-aligned Ni-alloy metal source/drain are demonstrated. Finally, the first set of studies to investigate the radiation response of antimonide p-MOSFETs for potential use in harsh environments such as for space and defense applications is conducted. Laser and heavy ion irradiation testing is performed and supported with simulations to understand the basic mechanisms of single-event-effects in these heterostructure antimonide p-MOSFETs.

Shashank Gupta, Ph.D. 2018
Research: Germanium Based Laser and Modulator for Photonic Interconnects.

Silicon photonics is considered to be a key enabling technology for future CMOS systems since it has the potential to alleviate the bandwidth-power-density bottleneck of electrical interconnects. In this work we are developing semiconductor beam structures for light emission and modulation applications. For example, we consider a strained crossed nanobeam structure for a low-threshold germanium laser. It includes a germanium (Ge) photonic crystal nanobeam resonator and a silicon nitride (SiN) stressor nanobeam in the perpendicular direction. While the photonic crystal nanobeam enables light confinement in a subwavelength volume with minimal optical loss, the SiN nanobeam induces high tensile strain in the small region where the optical mode is tightly confined. As maintaining a small optical loss and a high tensile strain reduces the required pumping for achieving net optical gain beyond cavity losses, this technique can be used to develop an extremely low-threshold Ge laser source. We are also developing a compact Ge electro-absorption modulator (EAM) based on Franz-Keldysh effect according to which an applied electric field causes band-tilting thereby increasing the absorption coefficient in the weakly absorbing regime. The Ge EAM devices are integrated in SOI Si platform. These devices have improved performance including higher modulation speed, higher efficiency and lower capacitance, owing to the strong confinement of optical and electrical field enabled by the submicron Ge/Si waveguide platform.

Raisul Islam, Ph.D. 2017
Research: Metal Oxide Carrier Selective Contacts for On-chip Embedded Photovoltaics.

In this work, a systematic study of transition metal oxide integration to thin c-Si solar cells as carrier selective contacts is presented. Thin c-Si solar cell technology is suitable for on-chip embedded photovoltaics to harvest energy from ambient light powering IoT systems for environmental, medical and agricultural monitoring. It has also the potential to be integrated with a TMD cell to result in high efficiency (> 30%) tandem cell on flexible substrate. Unlike the conventional Si PV cell, thin solar cell faces loss of absorption due to thinner absorber which can be mitigated by adopting light trapping technique. However, our simulation suggests that contact selectivity limits the performance significantly when the absorber gets thinner even if light trapping is adopted. Contact selectivity implies the ability of a contact to allow one type of carrier while blocking the other type and p-n junction provides this in a conventional PV cell. It is observed that when the absorber thickness gets smaller, significant performance improvement can be achieved by improving the contact selectivity beyond what is obtained from a p-n junction. In this work, transition metal oxides are introduced as carrier selective contacts to thin Si solar cell. Using oxides (NiO and TiO2) having asymmetric band offsets to Si, the contact selectivity of p-n junction solar cell will be shown to improve experimentally resulting in significant improvement in solar cell efficiency. Next, a heterojunction structure of solar cell is introduced using these oxides that does not require any high doped junctions inside the Si absorber. Removing high doped regions from the area and thickness constrained on-chip PV cell and replacing them with transparent oxides utilizes the absorber material efficiently. Detailed simulation study of the heterojunction structure is presented where the impact of metal Fermi level pinning on oxides and the doping of the oxides on device performance is studied. It is shown that characterizing the Fermi level pinning properties of these oxides is important. Therefore, we have studied the Fermi level pinning properties of NiO contact, a promising hole selective material, on Si experimentally. We also observe that doping plays a critical role in determining the performance of the oxides as selective contacts. Finally, a novel technique of introducing p-doping in NiO using UV/ozone treatment technique is shown. Both spectroscopic and electrical characterization suggests that UV/ozone treatment introduces Ni vacancy defects in NiO which dopes it p-type.

Gautam Shine, Ph.D. 2017
Research: Electron and Spin Transport in Disordered Nanoscale ContactsDevices

The continued scaling of semiconductor nanotechnology below 10 nanometers requires efficient injection of electrons across the interface between devices and contacts. In this talk we analyze tunneling in metal-semiconductor junctions to quantify the contact resistivity faced by future silicon technology nodes and propose solutions. First, we use density functional theory and GreenÕs functions to decompose the resistance into the loss due to tunneling and the loss due to band structure mismatch. Second, we use atomistic Monte Carlo simulations to construct probability distributions of contact resistivity in the sub-10 nm regime, where the discreteness of dopants is consequential. Finally, we assess the effectiveness of shifting the pinning of the Fermi level using interfacial layers inserted between the metal and the semiconductor. Our results demonstrate that barrier thinning with dopants is not robust to atomistic variation, but the addition of barrier lowering with interlayers provides the necessary reduction to meet scaling targets.

Ju Hyung Nam, Ph.D. 2016
Research: Monolithic integration of germanium-on-insulator platform on silicon substrate and its applications to devices.

Due to its higher carrier mobilities and lower optical bandgap, Ge has been considered as an attractive material for high performance CMOS and optical applications. High performance electrical and optical devices have already been demonstrated on a germanium-on-insulator (GOI) platform. To employ high performance GOI devices side by side with a silicon (Si) CMOS circuitry, monolithic integration of GOI platform on Si is needed. In this work, a lateral overgrowth technique for the monolithic integration of GOI on Si is demonstrated. Silicon dioxide is used as a growth mask. Ge is over-laterally grown from the growth windows defined in the SiO2 to form the GOI platform. The technique gives a high quality GOI platform. On the lateral overgrowth GOI, p-i-n and metal-semiconductor-metal (MSM) photodiodes are demonstrated. Ge MSM photodiodes typically show high dark current, due to the strong metal Fermi level pinning. To suppress the high dark current, photodiode with metal-insulator-semiconductor (MIS) contact is demonstrated using titanium oxide as a Fermi level de-pinning layer. The MIS contact allows transport of electrons freely but blocks holes to reduce dark current.

Ashish Pal, Ph.D. 2015
Research: III-V Material Integration in 1-Transistor Capacitor-Less DRAM

Scaling of the capacitor in present 1-Transistor 1-Capacitor DRAM (1T-1C DRAM) technology has become increasingly challenging. Recently the embedded DRAM technology has become mainstream where the logic transistor and the DRAM cell fabrication processes are integrated together. From this point of view, the 1-Transistor capacitor-less DRAM (1T-DRAM) technology is quite attractive since it stores charges inside the transistor body instead of a capacitor to distinguish between logic state Ô0Õ and Ô1Õ, thus eliminating the need of a capacitor. In this work we identify the inadequate charge storage capability as the main culprit for short retention time in silicon-based 1T-DRAM. We propose to use gallium phosphide (GaP) at source and drain (GaP-SD) which has a large valence band-offset (0.8-1 eV) and close lattice constant (0.37% mismatch) to silicon. This band-offset increases the hole storage capability of the transistor and its retention time while not affecting its speed of operations. Using TCAD simulations, we evaluate different GaP-SD 1T-DRAM structures suitable for commodity and embedded DRAM (for bulk and SOI) technology and show its superiority to pure silicon based 1T-DRAM in terms of scalability and the retention time performance. To fabricate GaP source-drain transistors, we first optimize the growth of a thin and strained GaP film on bulk Si substrate using MOCVD technique. We evaluate the GaP film and Si-GaP p-n heterojunction interface using different physical characterization techniques (SEM, XRD, AFM, TEM) and also by electrical characterization technique by forming a heterojunction diode. Next, long channel transistors on bulk silicon substrate with GaP source-drain and silicon channel are fabricated to show the proper functioning of GaP as source and drain material. Finally, using optical excitation as a method of hole generation, we confirm the enhanced hole storage capability of the GaP-SD transistor, thus validating the efficiency of the GaP-Si valence band offset.

Dave Sukhdeo, Ph.D. 2015
Research: Band-Engineered Germanium for CMOS-Compatible Light Emission.

While scaling a CMOS transistor to smaller dimensions increases speed and reduces power consumption, the opposite is true for scaling down the metal interconnects that link these transistors. CMOS-compatible on- and off-chip optical interconnects offer a promising solution to this new performance bottleneck and several key components such as waveguides, detectors and modulators have already been demonstrated. However, a practical silicon CMOS-compatible light source remains elusive. Germanium has been proposed as a laser gain material due to its inherent compatibility with CMOS technology, but this requires overcoming the limitations imposed by germaniumÕs indirect bandgap. In this work we present theoretical and experimental answers to these problems. We begin with a theoretical investigation of the relative merits of n-type doping and band engineering through tensile strain to determine which is more useful. We then show theoretically that while n-type doping is of limited benefit, using a large tensile strain can result in an efficient low-threshold germanium laser. From there we present new CMOS-compatible techniques for engineering large tensile strains in germanium. Firstly, we improve upon an existing microbridge technique to achieve up to 5.7% uniaxial tensile strain in germanium. This is the highest such strain ever reported and is sufficient to turn germanium into a direct bandgap semiconductor. Secondly, we present a completely new technique for engineering up to 1.1% biaxial strain in germanium microdisks. Finally, we discuss the implications of these theoretical and experimental achievements toward creating an efficient low-threshold germanium laser for use in CMOS-compatible on-chip light emission.

WooShik Jung, Ph.D. 2014
Research: Fluorine Passivation of Defects in Germanium Devices

In this work, passivation of Ge defect sites using fluorine (F) is proposed and investigated first. Fluorine, being the most reactive element in the periodic table has high potential to bond with the Ge defect sites, thereby eliminating their degenerate effects. But before incorporating F into the Ge defect sites, properties of Ge defects and its impact on electrical properties are thoroughly investigated. For the second part, the electrical effects of defects within bulk Ge are experimentally investigated, by intentionally inducing defects by Ge ion implantation. Here, the F is introduced to the defective Ge by ion-implantation, followed by additional thermal anneal step in order for F to bond with Ge defect sites. For the third part, this method is applied to n+/p Ge diode and Ge n-MOSFET fabrication, and the effects of F passivation are investigated in terms of electrical performance. In the fourth part, the effect of F passivation is further investigated in aspect of carrier lifetime through F treated Ge p-n diode.

Donguk Nam, Ph.D. 2014
Research: Strained Germanium Technology for On-Chip Optical Interconnects.

To alleviate the performance bottleneck in ICs, optical interconnects, which have already revolutionized long-haul communications, have recently gained much attention for on-chip applications. Over the past decade many of the key constituents of an on-chip optical interconnect system, such as high-performance photodetectors and modulators, have been demonstrated on a silicon-compatible platform. However, an efficient light source remains particularly challenging: silicon and silicon-compatible materials such as germanium (Ge) are not readily suitable for light emission because their band gaps are indirect. It has been proposed to use tensile strain to make GeÕs band gap direct and therefore suitable for light emission, however experimental realization has thus far been lacking. In this dissertation, we focus on developing an efficient silicon-compatible light emitter based on strained Ge technology. Starting from theoretical calculations showing how tensile strain can improve the light emission efficiency of Ge, we present several approaches for enhancing light emission from highly strained Ge on a CMOS-compatible platform. In the first part, we describe a thin film membrane technique in which a large residual stress in a tungsten layer is used as a stressor to induce a biaxial strain in a Ge membrane, upon which we have fabricated optoelectronic devices. In the second part, we introduce an approach to induce uniaxial strain that can potentially create a direct band gap in Ge wire using geometrical amplification of a small pre-existing strain. Lastly, we present a novel way to mimic double-heterostructure behavior within a single material, further enhancing light emission from Ge by capturing photo-generated carriers within a strain-induced potential well. Throughout this dissertation, we discuss the implications of these experimental achievements towards creating an efficient Ge laser for use in silicon-compatible optical interconnects.